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SI9978DW
Vishay Siliconix
SI9978
Configurable H-Bridge Driver
FEATURES
* H-Bridge or Dual Half-Bridge Operation * Cross-Conduction Protected * 20- to 40-V Supply * Current Limit * Static (dc) Operation * Undervoltage Lockout * ESD Protected * Fault Output
DESCRIPTION
The SI9978DW is an integrated driver for an n-channel MOSFET H-bridge. The mode control allows operation as either a full H-bridge driver or as two independent half-bridges. The DIR/PWM input configuration allows easy implementation of either sign/magnitude or anti-phase PWM drive schemes for full H-bridges. Schmitt triggers on the inputs provide logic signal compatibility and hysteresis for increased noise immunity. An internal low-voltage regulator allows the device to be powered directly from a system supply of 20 to 40 volts. All n-channel gates are driven directly from low-impedance outputs. The addition of one external capacitor per half-bridge allows internal circuitry to level shift both the power supply and logic signal for the high-side n-channel gate drives. Internal charge pumps replace leakage current lost in the high-side driver circuits to provide "static" (dc) operation in any output condition. Protection features include an undervoltage lockout, cross-conduction prevention logic, and overcurrent monitors. The SI9978DW is available in the 24-pin wide-body SOIC (surface mount) package, specified to operate over the industrial (-40 to +85C) temperature range.
FUNCTIONAL BLOCK DIAGRAM
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S-60752--Rev. D, 05-Apr-99 1
SI9978DW
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Voltage on pins 2-7 with respect to ground. . . . . . -0.3 to VDD + 0.3 V Voltage on pin 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 50 V Voltage on pins 17, 19, 21, 23 . . . . . . . . . . . . . . . . . . . . -0.3 to +60 V Voltage on pins 18, 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2 to 50 V Operating Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . -40 to +85C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150C Maximum Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . 150C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW
RECOMMENDED OPERATING CONDITIONS
V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +20 to 40 VDC RA, RB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 k
SPECIFICATIONS
Limits Test Conditions Unless Otherwise Specified Parameter Power
Supply Voltage Range Logic Voltage Supply Current V+ VDD I+ IDD = 0 mA 20 14.5 16 3 40 17.5 5 V mA -40 to 85C
Symbol
V+ = 20 to 40 V
Mina
Typb
Maxa
Unit
Inputs (DIR, PWM, EN, QS, MODE, BRK)
High-State Low-State High-State Input Current Low-State Input Current VIH VIL IIH IIL VIH = VDD VIL = 0 V -100 -50 4.0 1.0 10 -25 V
A
Outputs
Low-Side Gate Drive, High State Low-Side Gate Drive, Low State High-Side Gate Drive, High State High-Side Gate Drive, Low State Capacitor Voltagec Low-Side Switching, Rise Time Low-Side Switching, Fall Time High-Side Switching, Rise Time High-Side Switching, Fall Time Break-Before-Make Time FAULT, CL FAULT, CL Leakage Current VOL IOH IOL = 1 mA FAULT, CL = VDD 0.2 VGBH VGBL VGTH VGTL VCAP trL tfL trH tfH Rise Time = 1 to 10 V Fall Time = 10 to 1 V CL = 600 pF SA, B = 0 V V+ = 40 V 14 16 14 16 17.5 1 18 1 55 110 50 110 50 250 0.4 10 V A ns V
Protection
Low-Side Undervoltage Lockout Low-Side Hysteresis High-Side Undervoltage Lockout UVLL VH UVLH SA, B = 0 V 0.8 VDD 0.8 VDD-3.3 V V
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SI9978DW
Vishay Siliconix
SPECIFICATIONS
Limits Test Conditions Unless Otherwise Specified Parameter Current Limit
Comparator Input Bias Current Comparator Threshold Voltage IIB VTH tp tpd TA = 25C RA, RB = 100 k, CA, CB = 100 pF RA, RB = 100 k, CA, CB = 0.001 F CL = 600 pF -5 90 85 8 80 10 100 600 -0.2 100 5 110 115 12 120 A mV -40 to 85C
Symbol
V+ = 20 to 40 V
Mina
Typb
Maxa
Unit
One Shot Pulse Width Propagation Delay Notes:
s ns
a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. c. VCAP = (V+) + (VDD)
TRUTH TABLE H-BRIDGE MODEL
MODE 1 1 1 1 1 1 1 1 DIR/ INA 1 1 0 0 X X X X EN/ ENA 1 1 1 1 1 0 1 X QS/ INB 1 0 1 0 X X X X X X X X PWM/ ENB BRK 0 0 0 0 1 X 0 X X ILA+ L L L L L L ILB+ X X X X X X X X L L L L L L H L L L K L L L GTA H GBA L L GTB L L H L L H L L L 1 0 GBB CL/ FAULTB 1 1 1 1 1 1 FAULT/ FAULTA 1 1 1 1 1 1 Brake Disable Overcurrent Undervoltage on VDD Normal Operation Condition
HALF-BRIDGE MODEL
MODE 0 0 0 0 0 0 0 DIR/ INA 1 0 X X X X X EN/ ENA 1 1 0 0 1 X X QS/ INB X X 1 0 X X X PWM/ ENB 0 0 1 1 X 1 X BRK X X X X X X X X X X ILA+ L L L L ILB+ L L L L X GTA H L L L L X L GBA L H L L L X L GTB L L H L X L L GBB L L L H X L L 0 CL/ FAULTB 1 1 1 1 1 1 0 FAULT/ FAULTA 1 1 1 1 Overcurrent on A Overcurrent on B Undervoltage on VDD Normal Operation Condition
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S-60752--Rev. D, 05-Apr-99 3
SI9978DW
Vishay Siliconix
PIN CONFIGURATION
PIN DESCRIPTION
Pin 1: VDD VDD is an internally generated voltage. It is connected to this pin to allow connection of a decoupling capacitor. A minimum of 1 F is recommended. Pin 2: EN/ENA The EN input allows normal operation when at logic "1", and turns all gate drive outputs off when at logic "0". When the mode pin is at logic "1", EN controls the entire H-bridge. When the mode pin is at logic "0", this pin becomes the ENABLE pin for half-bridge A. Pin 3: DIR/INA The function of this pin is determined by the MODE pin. When the MODE pin is at logic "1", it is the DIR pin, and when MODE is at logic "0", it is the INA pin. As the DIR input, it is the direction control for the H-bridge, and determines which diagonal pair of power MOSFETs is active. A logic "1" turns on GTA and enables GBB, while a logic "0" turns on GTB and enables GBA. When implementing an anti-phase PWM control, the DIR input serves as the PWM input. As the INA pin, it is the input that controls the "A" half-bridge. When at logic "1", the high-side MOSFET is turned on, and when at logic "0", the low-side MOSFET is turned on. Pin 4: PWM/ENB With the mode pin at logic "1", this pin is the PWM input. It controls the switching of the active diagonal pair. A logic "1"
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turns the active MOSFETs on, while a logic "0" turns it off. The QS input determines whether the bottom or both bottom and top MOSFETs are switched. When implementing an anti-phase PWM control, the PWM input is connected to a logic "1". When the mode pin is at logic "0", this pin becomes the ENABLE pin for half-bridge B. Pin 5: QS/INB With the mode pin at logic "1", this input determines whether the bottom MOSFETs of the H-bridge or both bottom and top MOSFETs switch in response to the PWM signal. A logic "1" on this input enables only the bottom MOSFETs. This is the default condition as this pin is pulled up internally. When this pin is pulled to ground, both the bottom and top MOSFETs are enabled. This input controls the B half-bridge when the MODE pin is at logic "0". When at logic "1", the high-side MOSFET is turned on, and when at logic "0", the low-side MOSFET is turned on. Pin 6: MODE This input determines whether the SI9978 functions as an H-bridge or as two independent half-bridges. When the MODE pin is at logic "1", the SI9978 functions as an H-bridge, and when MODE is at logic "0", it functions as two independent half-bridges. Pin 7: BRK When this input and MODE are at logic "1", both bottom gate drives are switched high, turning on the bottom MOSFETs. When this input is at logic "0", the SI9978 operates normally.
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SI9978DW
Vishay Siliconix
Pin 8: CL/FAULTB This is an open drain output which is active low. When the MODE pin is at logic "1", this pin functions as CL and indicates that the H-bridge is in current limit. It stays low for the duration of the current limit one-shot. With the MODE pin at logic "0", it serves as the FAULT output for half-bridge B to indicate when an undervoltage or overcurrent condition is detected. When indicating an overcurrent condition, the output stays low for the duration of the current limit one-shot. The FAULT output resets automatically when the condition clears. Pin 9: FAULT/FAULTA This is an open drain output which is switched low when an undervoltage or overcurrent condition is detected. When indicating an overcurrent condition, the output stays low for the duration of the current limit one-shot. When the MODE pin is at logic "1", this pin is the H-bridge FAULT output. With the MODE pin at logic "0", it serves as the FAULT output for half-bridge A. The FAULT output resets automatically when the condition clears. Pin 10: NC No internal connection. Pin 11: RA/CA The timing resistor and capacitor for the current limit one-shot are connected to this pin. The values of the resistor and capacitor determine the off time set by the one-shot. The one-shot is triggered when the current limit comparator detects an overcurrent condition. Pin 12: RB/CB The timing resistor and capacitor for the current limit one-shot are connected to this pin. The values of the resistor and capacitor determine the off time set by the one-shot. The one-shot is triggered when the current limit comparator detects an overcurrent condition. Pin 13: ILA+ and Pin 14, ILB+ These are the overcurrent sense inputs. Internally, they are connected to the noninverting inputs of the current limit comparators. Externally they are connected to the source(s) of the low-side MOSFET(s) and the current sense resistor. Pin 15: GND The GND pin is the ground return for V+ and the ground reference for the logic. Also, this is the ground reference input for the current limit comparators and is connected to the ground side of the internal 100-mV references. This pin should be connected directly to the ground side of the current sensing resistors. Pin 16: GBB and Pin 20, GBA These pins drive the gates of the low-side power MOSFETs. Pin 17: GTB and Pin 21, GTA These pins drive the gates of the high-side power MOSFETs. Pin 18: SB and Pin 22, SA These are the source connections of the high-side power MOSFETs, the drain of the external low-side power MOSFET, the negative terminal of the bootstrap capacitor, and the output for each half-bridge. Pin 19: CAPB and Pin 23, CAPA These are the connections for the positive terminals of the bootstrap capacitors CBA and CBB. A 0.01-F capacitor can be used for most applications. Pin 24: V+ This is the only external power supply required for the SI9978DW, and must be the same supply used to power the H-bridge it is driving. The SI9978DW powers the low-voltage logic, low-side gate driver, and bootstrap/ charge pump circuits from self-contained voltage regulators which require only a bootstrap capacitor on the CAP pins. No voltage sensing circuitry monitors V+ directly; however, the low-voltage, internally generated supply and the bootstrap voltage (which are derived from V+) are directly protected by undervoltage monitors.
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S-60752--Rev. D, 05-Apr-99 5
SI9978DW
Vishay Siliconix
APPLICATIONS
FIGURE 1. Basic H-Bridge Circuit
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